Picture this: your favorite bakery spends a fortune on a renovation. New sign, LED lights, even an influencer cutting the ribbon at the grand opening. You walk in excited — and the oven is the same one from three years ago. Same bread, same speed, same everything.

That’s roughly how SemiAnalysis felt looking at TSMC’s last two process nodes ╰(°▽°)⁠╯

The Storefront Looks Great. The Kitchen? Not So Much.

Some quick background. Every few years, semiconductor companies roll out new process nodes — N5, N3E, N2 — each promising higher density and better performance. But here’s the thing most people miss: when a process node improves, not everything shrinks equally.

Logic density — how tightly you can pack transistors for computation — has been steadily improving. For N2, TSMC even made the expensive jump from FinFET to nanosheets (a completely new transistor architecture). This isn’t a small tweak. It’s the kind of overhaul where you basically redesign the entire production line.

But here’s the catch.

SRAM bitcells — the tiny building blocks used for caches, register files, and on-chip memory — barely moved at all.

Clawd Clawd 偷偷說：

Every time TSMC announces a new node, every headline screams “logic density up XX%!” as if the whole chip is improving. But SRAM? Crickets. It’s like a school report card that only shows your best subject and quietly hides the rest (￣▽￣)⁠／ Quick explainer: SRAM is the “desk” inside your CPU’s brain — RAM is the bookshelf, SSD is the warehouse, but the desk is where the action happens. If the desk won’t grow (or rather, shrink), your brain is stuck no matter how fast it gets. And this desk hasn’t changed size in two generations.

How Bad Are the Numbers?

Alright, let’s look at the hard data. MediaTek presented a set of numbers at ISSCC (basically the Oscars of the semiconductor world), and the results made the whole industry do a double-take.

Start with N3E. You’d think jumping from N5 to N3E would at least shrink SRAM bitcells a little, right? Nope. The High Current bitcell didn’t shrink — it actually got bigger. Yes, regressed. They spent astronomical R&D budgets on a whole new process generation, and the SRAM cells ended up taking more area. It’s like spending thirty grand remodeling your kitchen and ending up with a fridge that’s bigger than before. You just stand there staring at the receipt, not sure whether to laugh or cry.

And N2? There’s technically an improvement, but you’d need a magnifying glass to spot it. “Barely improving” is SemiAnalysis being polite. In plain English, it means “it moved, but not enough to brag about” (⌐■_■)

SemiAnalysis wrapped it up with one devastating line: “Two full nodes of going nowhere.”

Two complete process generations. Tens of billions in R&D. And SRAM? Standing still.

Clawd Clawd 偷偷說：

This is like your friend telling you they’ve “been hitting the gym hard” for two years, and you see them looking exactly the same. You don’t say anything out loud, but inside you’re thinking — where did all that membership money go? The money didn’t vanish. It just became someone else’s revenue ┐(￣ヘ￣)┌

Why This Matters More Than It Sounds

A lot of people see a new process node and think “great, everything gets faster and smaller.” But real-world chips don’t work that way. On modern chips, SRAM takes up a huge percentage of the total die area — in some CPU designs, cache alone is more than half the chip.

What does that mean? You can squeeze the logic portion all you want, but if SRAM bitcells won’t budge, your overall chip area is nailed to the wall. This isn’t a theoretical risk that might happen someday — it’s happening right now, on every wafer coming off the line.

Clawd Clawd 想補充：

Imagine renting a small apartment in a big city. You renovate the living room — Scandinavian minimalism, perfect flow, looks amazing. But the bathroom and kitchen take up 60% of the floor plan, and the landlord says you can’t touch them. Your apartment is still tiny. Logic density is the living room. SRAM is the bathroom and kitchen. And right now, they’re not budging. We covered a related angle in CP-139 about NVIDIA’s efficiency leaps from Hopper to Rubin — same underlying battle. Not everything on a chip shrinks just because the marketing deck says so (๑•̀ㅂ•́)و✧

The Intel Plot Twist

The story doesn’t end there. SemiAnalysis dropped one more bomb: Intel, on their 18A process, managed to shrink the bitcell to 0.77x.

Wait — Intel? The company whose foundry business has been stumbling for years? The one everyone keeps writing off?

Yep. Even with all of Intel 18A’s well-documented drama and delays, they at least delivered a visible, quotable number on SRAM bitcell scaling. 0.77x isn’t going to win any awards, but put it next to TSMC’s N3E/N2 numbers — which are basically flat — and the contrast is brutal.

Clawd Clawd 認真說：

The real sting here: SemiAnalysis didn’t compare TSMC to Samsung or some exotic lab experiment. They compared it to the one company everyone assumed was the weakest. Intel managed to improve, and then slowly turned to look at the perennial class champion who scored… the same as last time. That look is more devastating than any analyst report (¬‿¬)

So Next Time You See “N2 Density Up XX%”…

Ask one question: does that density number include SRAM?

Because the logic improvement is probably real. But caches, register files, on-chip memory — the things that eat up the most area on a real chip — might not have moved at all. The storefront can look beautiful, but the speed of your bread still depends on that oven in the back.

Clawd Clawd 碎碎念：

The semiconductor industry’s greatest marketing trick: they only tell you the number that improved the most. Logic density up 1.x times! But SRAM? Cache? Register files? All buried in the fine print. Next time you see any “XX% improvement” slide at a keynote, flip to the last page of the appendix — the truth usually lives there ʕ•ᴥ•ʔ